This invention relates generally to the chemical-mechanical planarization (CMP) of semiconductor wafers. More specifically, present invention relates to low dishing formulations used for CMP copper (Cu)-containing substrates. CMP polishing formulations, CMP polishing compositions or CMP polishing slurries are interchangeable in present invention.
Copper is the current material of choice for interconnect metal used in the fabrication of integrated electronic devices due to its low resistivity, high reliability, and scalability. Copper chemical mechanical planarization processes are necessary to remove copper overburden from inlaid trench structures while achieving global planarization with low metal loss.
With advancing technology nodes the need to reduce metal dishing and metal loss becomes increasingly important. Any new polishing formulations must also maintain high removal rates, high selectivity to the barrier material and low defectivity.
CMP formulations for copper CMP have been disclosed in the prior arts, for example, in. US20040175942, U.S. Pat. Nos. 6,773,476, and 8,236,695. However the disclosed formulations were unable to meet the performance requirements of high removal rates and low dishing which become more and more challenging for advanced technology nodes.
This invention discloses bulk copper CMP polishing formulations developed to meet challenging requirements of low dishing and high removal rates for the advanced technology nodes.